The present invention generally relates to a memory bank comparator system for use in a memory system incorporating a plurality of memory banks. The present invention more particularly relates to such a system for use in a memory system including a plurality of dynamic random access memory banks and which, determines on a cycle-by-cycle basis if a memory address is a valid address, which memory bank is being addressed, whether memory bank interleaving is possible, and what type of memory access cycle is required.
Memory systems are well known in the art. In applications were a large amount of memory space is required, such as in personal computer applications, memory systems may include more than one memory bank. Also, dynamic random access memories are extremely popular in such applications because of their extremely high memory density.
In a typical system, when a byte of data is to be stored, each memory bank is provided with the same memory address, first a row address, and then a column address. The particular memory location is selected with the application of first, a row address strobe signal and then a column strobe signal being applied to the proper memory bank. A write enable signal is then applied to each memory back which is maintained as the byte of data is conveyed to each bank. Because only one bank is enabled to receive the row and column address, the byte of data is stored within its own unique storage location.
Enhancements have been added to this general memory accessing procedure to improve upon memory access time. For example, a paging mode has been adopted wherein, instead of providing a newly generated row strobe signal during each cycle, the row strobe signal is maintained while new column addresses and column strobe signals are generated. The row strobe signal is maintained until a new row address is detected. This reduces addressing time and has been found to be advantageous since data is normally stored in bytes with a given memory bank being accessed for a number of consecutive cycles.
Another enhancement has been the interleave mode. Interleaving is the practice of storing consecutive bytes of data in alternating or successive memory banks. This practice speeds up memory access because it counters the effect of row address strobe precharge. Hence, while a byte of data is stored in a memory bank, the row address strobe for the previous memory bank may be precharged fully and be ready for the next byte of data to be entered into that memory bank.
In addition to the foregoing, dynamic random access memories have been improved so that such devices are available in different types with each type corresponding to a respective different storage capacity. There are basically three different dynamic random access memory types, a 256 Kb type, a 1 Mb type, and a 4 Mb type. These different memory types afford flexibility to the ultimate user who may wish to tailor the storage size to a particular application or to increase the storage size of an existing system. Unfortunately, each memory type requires a different type of access cycle. This is mainly due to the need for a different number of address bits for each type. For example, the 256 Kb type requires nine row and nine column address bits, the 1 Mb type requires ten row and ten column address bits, and the 4 Mb type requires eleven row and eleven column address bits. Also, memory type is important from the aspect of interleaving, since interleaving is only possible between memory banks of the same type.
Hence, from the foregoing, it can be seen that multiple bank memory systems require memory management. One important aspect of such memory management is to determine which bank is to receive a byte of data. Another important aspect is to determine if interleaving is possible if interleaving is enabled. A still further aspect is to determine the type of memory bank in which the byte of data is to be stored to enable the selection of the proper cycle type. Lastly, it is important to be able to determine if the memory address is a valid address, in other words, if there is an available storage location in one of the memory banks corresponding to the memory address.
One disadvantage in the prior art has been that such systems generally require the interleaving configuration to be determined at the time the system is configured. This places an extreme restriction on the flexibility of the system and does not permit memory bank interchanges after a system is configured. Also, although interleaving cycle type may be determined, such interleaving may not be possible under a given set of circumstances, such as, for example, when a memory bank to be interleaved is full. This can result in the system not knowing where to store a given byte of data.